Electrical isolation of semiconductor integrated transistors from one another can be achieved by laterally (in the plane of the wafer) isolating "active" regions of the device with insulating material. Two techniques are common: 1) selectively oxidizing wafer silicon surrounding the active region (known as "LOCOS", or Local Oxidation of Silicon), or 2) depositing insulating material, such as silicon dioxide ("oxide") in a trench (or "bathtub") around the active region. The former, selectively oxidizing to form a field (isolation) oxide region, is discussed in the main hereinafter.
One known technique of forming isolation oxide around a diffusion area is Local Oxidation Of Silicon ("LOCOS"). In the typical LOCOS process, a mask (e.g., nitride) is applied to the wafer, a trench is etched, the wafer is heated, and oxide "grows" predominantly in the trench. In this manner, an isolation structure is created that extends both into the wafer and some height above the wafer. In a "semi-recessed" version of this process, the height of the oxide structure above wafer level is approximately 45% of the total thickness of the as-grown oxide. In a "fully-sunk" ("fully-recessed") version of this process, the isolation structure can grow to a height of about 25-45% of the total oxide thickness, above wafer level. No matter how it is grown, the resulting oxide structure has a prominent portion above wafer level, resulting in an irregular top surface wafer topography. It is known to polish the wafer to remove the prominent portion of the isolation structure, but this usually involves steps ensuring that the isolation oxide structure does not become gouged out below wafer level, especially if a polish stop (e.g., nitride cap or mask layer) is employed to protect the diffusion region.
LOCOS is described in U.S. Pat. Nos. 4,897,364, 4,903,109 and 4,927,780, incorporated by reference herein.
Subsequent deposition of polysilicon ("poly"), which may typically follow the LOCOS process, usually places poly on top of the diffusion areas and on top of the LOCOS oxide. The top of the poly is typically 3000-4000 .ANG. above the level of the diffusion area, simply because of the normal poly thickness. The poly that is located above the LOCOS region is another 4000-5000 .ANG. above the level of the top of the poly over the diffusion region, simply because of the prominence (not polished) of the oxide in the LOCOS area. For this reason, the difference in height between the diffusion area and the poly over the LOCOS area can be as great as 8000 .ANG.. This large difference in height is very undesirable, but is the natural consequence of the process as currently implemented.
FIG. 1 graphically illustrates the situation, and shows a semiconductor device 110 having a silicon wafer 112, a diffusion area (active region) 114 and field oxide areas (e.g., LOCOS) 116 adjacent the diffusion region 114. Inasmuch as the field oxide areas 116 are thermally formed, they exhibit a raised topography at the wafer surface. U.S. Pat. Nos. 4,892,845, 4,897,150, 4,918,510, 4,935,378, 4,935,804, 4,954,214, 4,954,459 and 4,966,861 illustrate structures of this general type, and are incorporated by reference herein.
A polysilicon layer 118 is deposited over the diffusion area 114, and extends from the diffusion region 114 to at least partially over the adjacent field oxide areas 116. The polysilicon layer is shown segmented, discontinuous at the center of the diffusion region 114, but is can be contiguous and extend entirely over the diffusion region. An overlying, generally-conformal insulating oxide layer 120 is deposited over the wafer. Vias 122a and 122b are formed through the insulating oxide 120--one via 122a for making contact with the diffusion area 114 at wafer level, and another via 122b for making contact with the poly 118 over the field oxide area 116. Evidently, the vias 122a and 122b are of unequal depth (even if the insulating layer 120 is subsequently planarized), which causes problems with subsequent via-filling. As mentioned hereinabove, the via 122b to the poly over the field oxide area is shallower by the height (above wafer level) of the field oxide area plus the poly thickness. The problems associated with filling vias of unequal depth are discussed described in commonly-owned U.S. Pat. Nos. 4,708,770 and 4,879,257, incorporated by reference herein.
Another problem is that the top surface of the insulating layer 120 is highly irregular (not smooth and non-planar). This irregular top surface topography will propagate through subsequent depositions, if left unchecked, making subsequent processing steps more complicated (e.g., requiring a planarization step).
As mentioned above, planarizing the isolation and diffusion regions (e.g., by polishing back the oxide prominence) is complicated by the different hardnesses of the isolation oxide and the (essentially silicon) diffusion region. The diffusion region, essentially native silicon, is softer than oxide (SiO.sub.2), but a polishing stop can be incorporated over the diffusion region. In either case, material hardness differences are the problem.
Consider, for example, the case of a "fully-sunken" LOCOS oxide structure exhibiting a "Bird's-Beak", as shown in FIG. 4A. In the typical implementation of polishing the LOCOS structure (to remove the "Bird's-Head"), the polishing is stopped before the Bird's Beak is totally removed. This is objectionable, because the Bird's-Beak extends laterally into the diffusion area in the polished structure, as shown in FIG. 4B. The bird's-beak is one of the most objectionable aspects of conventional dielectric isolation schemes, and a polish technique that does not effectively remove this structure, without resorting to deposited dielectric films, is lacking in utility.